CS355 Sylabus

# Circuit Timing

• A very important aspect in the design of sequential circuits is timing

Sequential circuits - such as the D-latch - have active and inactive periods.

 During the active period of a circuit, the output changes when the value of the input is changed. The output of a circuit will not change during the inactive period.

• For example, the D-latch circuit:

is active during the time that the Write signal is 1.

You can try this hands on with the following circuit file: click here

• Toggle key 3 so that the Write signal is 1
• Then toggle key 2 repeatedly. This changes the input of the D-latch.
• You will see the D-latch output change along with the input....

• We have basically discovered that the D-latch can be in 2 states:

• Active state: the output "follows" the input, i.e., the output changes when the input changes.
• Inactive state: the output does not follows the input, i.e., the output remains unchange no matter what happens to the input.

The D-latch in the above figure is:

• in the active state when the write signal (clock) is at level 1.
• in the inactive state when the write signal (clock) is at level 0.

• Latches are by definition level active devices.

In other words: a latch is active when the write signal (clock) is at a certain level (1 or 0)

You saw that the following D-latch is level-active for Write = 1

It is very easy to make a D-latch that is level-active for Write = 0, just insert a NOT gate before the Write signal:

• The computer operates in cycles, you may have guessed that since you knew that about the instruction execution cycle from CS255 ( click here)
• The device that control the "rhythm" of the computer is a clock

A clock is basically a pacing device and emits a regular pattern or square wave, that looks like this:

• The following figure shows the moments when the clock value is equal to 1, i.e., the periods when the D-latch will be active:

From this figure, one would clear see why latches are called "level-active" devices - the are active when the clock (write signal) is leveled...

• The D-latch is a memory element and it's output "captures the input value" when the Write signal is equal to 1.

Now, what happens when the input signal fluctuates while the Write signal is equal to 1 ???

Well, then what got captured will not be certain !!!

To ensure that the correct value is captured, the input value must be kept stable (constant) as long as he Write signal is equal to 1 (because otherwise, the circuit cannot ensure (guarantee) that the intented value will be captured).

(This may be analogous to a situation when you have exactly 1 min to make up your mind to buy something or not. If you keep changing your mind (yes, no, yes, no, etc) within that minute, it is possible for the system to record a wrong decision.

On the other hand, if you keep saying "yes" all the time for the whole minute, there is no way the system will record a different answer.)

• Since D-latches are level active devices, then to ensure that the correct value is written into a latch, the CPU must keep the input signal constant for the entire duration when the D-latch is active.

The fact is: the longer the CPU must keep the signal constant, the longer it takes to complete a CPU cycle and the slower the CPU will run.

You will get a faster CPU if the register has a faster write time, i.e., a shorter active period.

You can a shorter active period by shortening the clock period:

• A much better way to shorten the write time of memory device is to design memory devices that are edge active.

Recall that a memory device is active if the output changes then the input is changed.

An edge-active device is active during the period when the clock changes from 0 -> 1 or from 0 -> 1.

For example, the following figure shows the active period of an edge-active device:

You can clearly see that such a device is has a much shorter active period. These memory elements are much faster than D-latch memories.

• The question is how can we construct a edge-active memory device...

Consider the following circuit (which is called a D-flipflop):

If you look closely, you can see it consists of 2 D-latches. The first D-latch is active when the Write (clock) signal is 1 and the second D-latch is active when the Write (clock) signal is 0. The Q-output of the first D-latch is used as input to the second D-latch.

• Consider now the period that this device is active and we can conclude the following:

So one can conclude that the D-flipflop cannot be a level-active device...

• You can verify this fact for yourself using the following logic-sim circuit program: click here

• Use key 1 to toggle the clock to 0 or 1.
• While clock = 0, use key 0 to change the input continuously. The output remains unchanged.
• While clock = 1, change the input continuously again. The output also remains unchanged.

• Yet, the circuit is a one-bit memory. Just set the input with key 0 to 1 or 0, then toggle key 1 twice. You will see the output become equal to the input.

• The D-flipflop is an edge-active device and has an incredably short active period - because the time that takes for an electic signal to go from 0 -> 1 or from 1 -> 0 is in the order of nano-seconds

Observation:

• Look carefully at the circuit:

• Notice that the first stage is active when write (clock) = 1

Whatever the value is stored in the first stage, the second stage will copy it !

• The last value that the first stage will record is the one that is at its input during the transistion of the clock from 1 ⇒ 0

• In other words:

 The interval of "insecurity" for this D-flipflop is the transistion of the clock from 1 ⇒ 0

• This immersely fast write time manifest itself in the difference between the following 2 circuits.

• The first circuit is a cascaded series of D-flipflips:

Due to the immensely short write period, each D-flipflop will capture (and store) the current value of its preceeding register and the result is shifting 1 bit for every clock signal.

You can experiment with this circuit with the following logic-sim circuit file: click here.

• If we replace the D-flipflops with D-latches, the behaviour is completely different.

Because the D-latches are level-active, the input signal will have the time to reach the output of the first D-latch and immediately enter the input of the second D-latch and changes the output of the second D-latch. A few nano-second later, the output of the second D-latch is changed which will immediately change the input of the 3rd D-latch, and so on. So the result is: after a (very short time, several 100s nano seconds), all outputs are changed - because all D-latches remain active for the entire duration of the period when the Write signal = 1.

You can also experiment this with another logic-sim circuit file: click here. The circuit has also been shown in class....

• Importance of a short active period

• Consider the following circuit:

• Suppose Q = 1:

• After 1 clock period, the D-flipflop will capture the input (0):

Notice that the input has changed to 1 !!!

• After another clock period, the D-flipflop will capture the input (1):

Notice that the input has changed to 0 !!!

• And so on

• Example Program: (Demo above code)

How to run the program:

 Right click on link and save in a scratch directory To compile:   cs355sim loop-dff To run:          ./simex

• Now consider the same circuit, but using a D-ltach:

Fact:

• The circuit is unstable !!!

Because:

 The D-latch will be active for a relatively long time (long in terms of electrical current speed)

• When the D-latch is active, the output can change when the input changes

• An change in the output will cause a change in the input

• And so on....

• Result:

 The value of the output will never settle on a fixed value... I.e.: the output will alternate between 0 and 1 indefinitely

• Example Program: (Demo above code)

How to run the program:

 Right click on link and save in a scratch directory To compile:   cs355sim loop-d-latch To run:          ./simex

• Analogy

• A good analogy that explain the difference in havavior is:

 Shutter speed of a camera

• The input of a memory elements (a D-latch or a D-flipflop) is the lens of a camera

• The output of of a memory elements (a D-latch or a D-flipflop) is the image that the camera takes.

• The active period of a memory elements (a D-latch or a D-flipflop) is the duration that the lense is open (a.k.a., shutter speed)

• A D-latch is like a camera with a long shutter speed

A D-flipflop is like a camera with a very short shutter speed

• In this setup:

The analogy is:

 The first "camera" takes a picture of the input The 2nd "camera" takes a picture of the image recorded by the first "camera" The 3rd "camera" takes a picture of the image recorded by the 2nd "camera" The 4th "camera" takes a picture of the image recorded by the 3rd "camera"

• If the shutter speed is long, then all camera will display the same image (which is the "image" of the input)

Demo: shift-reg-D-latch.cc

• If the shutter speed is very short, then you will see this effect:

 Camera 1 (D-flipflop 1) captures the input Camera 2 (D-flipflop 2) captures the image (= output) of camera 1 (D-flipflop 1) Camera 3 (D-flipflop 3) captures the image (= output) of camera 2 (D-flipflop 2) Camera 4 (D-flipflop 4) captures the image (= output) of camera 3 (D-flipflop 3)

Demo: shift-register.cc