CS355 Syllabus & Progress

# CS355 Syllabus & Progress

Material covered are displayed in blue.

You can run the circuit examples by first saving the file in your own directory and then use logic-sim to run the circuit. To save an example from a webpage, do the following in Netscape:

```     Click File -> Save As
Complete the file name in the "Selection" box
(Make sure you specify the right directory name and file name !)
Click OK when the file name is right
```

Search the syllabus:

1. Logic elements and Boolean Algebra

2. Switching Circuits... how the CPU transports values from one place to another...
• Comment: you may have heard that a computer is one big switch... you will soon find out why.....

• Example use of a (many-to-one) multiplexor: switching registers to ALU - click here

• Example use of a decoder: select a register for writing: click here

3. Arithmetic (and Logic) Circuits.... see what the ALU look like

4. Sequential Circuits

5. Finite State Machines
• Side note:
• A computer is a FSA, with a huge number of states
• The number of states is equal to 2N where N is the number of bits of memory in the main memory and other storage (disks, tapes, CD-roms, etc)

6. Bi-directional Transfer

7. Memory Organization

8. CPU Micro Architecture
• The various data forwarding paths within the simple datapath: click here

Demo: cs355-demo-dp1
Demo: cs355-demo-dp2

9. Micro-programming:

10. The system bus:

11. IO Communication

You should now know how the entire computer works. The only things left to discuss are the bells and whistles that make the computer runs faster (and safer)...
12. Pipeline design

• How the Basic Pipelined CPU executes an ALU instruction:

• How the Basic Pipelined CPU executes a Memory access instruction:

• How the Basic Pipelined CPU executes a Branching instruction: click here

• Some problems you see in the Basic Pipelined CPU:
1. Data Hazard: old value of registers can be used in computation.
2. Control Hazard: branch delay of three instructions is unacceptable

• The Read after Write Data Hazard in ALU instructions:
• Solving the Read after Write Data Hazard in ALU instruction with Data Forwarding hardware: click here

• Control Hazard:
• Recall that the basic pipeline will fetch (and execute) three instructions before it actually branches: click here

13. Cache memory:

• Type of cache architectures:
1. Associative: very flexible and very expensive to make.
2. Direct-Mapped: cheap, but absolutely no flexibility.
3. Set-Associative: economical and some flexibility.

• The Set-Associative Cache: combination of Associative & Direct-Mapped
• Consists of K Direct-Mapped caches.
• Each entry or "slot" in cache can cache K words at the same location in K different pages: click here.

14. Parallel Computers

15. SIMD - Single Instruction (stream) and Multiple Data (stream) computers:

16. GPU-programming using the CUDA programming language:

17. MIMD (general multi-processors) computers
• The 2 different MIMD computers (shared memory MIMD and message-passing MIMD): click here

• CPU-to-Memory interconnection networks of Shared Memory MIMD computers:

18. Programming Shared Memory MIMD using Posix threads:

19. Programming Shared Memory MIMD using the OpenMP API: