CS355 Syllabus & Progress

# CS355 Syllabus & Progress

Material covered are displayed in blue.

You can run the circuit examples by first saving the file in your own directory and then use logic-sim to run the circuit. To save an example from a webpage, do the following in Netscape:

```     Click File -> Save As
Complete the file name in the "Selection" box
(Make sure you specify the right directory name and file name !)
Click OK when the file name is right
```

1. Logic elements and Boolean Algebra

2. Switching Circuits... how is the CPU wired...
• You may have heard that a computer is one big switch... you will soon find out why.....
• Example use of a (many-to-one) multiplexor: switching registers to ALU - click here
• Example use of a decoder: select a register for writing: click here

3. Arithmetic (and Logic) Circuits.... see what the ALU look like

4. Sequential Circuits

5. Finite State Machines (class notes, not in book)
• Side note:
• A computer is a FSA, with a huge number of states
• The number of states is equal to 2N where N is the number of bits of memory in the main memory and other storage (disks, tapes, CD-roms, etc)

6. Bi-directional Transfer (class notes, not in book)

7. Memory Organization

8. CPU Micro Architecture

9. Micro-programming:

Is you understand everything so far, congrats... You now know exactly how the computer works when it executes a program. The only thing that you don't know about the computer is how the CPU and memory (and IO devices) communicate with each other. We will fix that next....
10. The system bus:

11. IO Communication

You should now know how the entire computer works. The only things left to discuss are the bells and whistles that make the computer runs faster (and safer)...
12. Pipeline design
• The RISC phylosophy
• Modification to simplify pipeline design:
• Fixed size instruction
• Limited number of instructions that access memory. Only the following instructions will access memory:
• st: store (write data to memory)
• Reduced number of addressing modes, supports on immediate, direct and indirect with one index. Multiple indices can't be used.
• Computer instructions can be broadly categorized as follows:
• Memory instructions: ld and st (see above)
• Distinguishing feature: they access the memory
• Branching instructions: bra, bne, call, ret, etc., etc.
• Distinguishing feature: they change the PC so that the next instruction fetch is not the one at the "next memory location".
• ALU instructions: add, sub, mult, div, and, or, etc.
• Distinguishing feature: they can complete execution without accessing memory and the next instruction is located right after the currect one.

• How the Basic Pipelined CPU executes an ALU instruction:
• How the Basic Pipelined CPU executes a Memory access instruction:
• How the Basic Pipelined CPU executes a Branching instruction: click here

• Some problems you see in the Basic Pipelined CPU:
1. Data Hazard: old value of registers can be used in computation.
2. Control Hazard: branch delay of three instructions is unacceptable

• Read after Write Data Hazard in ALU instructions:
• Solving the Read after Write Data Hazard in ALU instruction with Data Forwarding hardware: click here

• Control Hazard:
• Recall that the basic pipeline will fetch (and execute) three instructions before it actually branches: click here

13. Cache memory:
• Cache: a very fast memory module placed near the CPU: click here.
• The cache memory can hold a part of the content of the memory.
• Cache can speed up program execution significantly due to program locality.
• Type of caches:
1. Associative: very flexible and very expensive to make.
2. Direct-Mapped: cheap, but absolutely no flexibility.
3. Set-Associative: economical and some flexibility.
• The Associative Cache:
• The memory is divided up into "words".
• each "word" is 32 bits.
• The address of a "word" is called a "block number".
• Each entry or "slot" can cache a word (32 bits).
• Use the "block number" to identify entries cached: click here for an example.
• When CPU sends out the read instruction, the cache will use the address values sent out by the CPU to look the block number up in the cache. If the block number is found, the cache returns the value to the CPU, otherwise, the cache will start a memory read cycle to get the data for the CPU.
• One problem: a serial search will take too long.
• Strength: a slot can cache any word from any memory location (flexible).
• Weakness: uses one compare circuit per slot. This make the Associative Cache very expensive....
• The Direct-Mapped Cache:
• The memory is also divided into "blocks"
• But each "block" is the same size as the entire direct mapped cache.
• Each entry or "slot" in cache can only cache a word (32 bits) at the same location in a page: click here.
• Strength: lower cost. Main cost is the multiplexor circuits, which is relatively cheaper to make.
• Weakness: a slot in the cache can only cache a set of specific word from memory (not flexible).
• The Set-Associative Cache: combination of Associative & Direct-Mapped
• Consists of K Direct-Mapped caches.
• Each entry or "slot" in cache can cache K words at the same location in K different pages: click here.